1. Field of the Invention
The present invention relates to a fuse circuit and a semiconductor integrated circuit device and, more particularly, to a fuse circuit used at low voltage and a semiconductor integrated circuit device.
2. Description of the Related Art
A fuse circuit, with a fuse which may be blown or not blown as desired, is used for various internal processing or specification setting purposes in a semiconductor integrated circuit device and, for example, to implement redundancy to replace a defective cell in a DRAM (Dynamic Random Access Memory), or to customize a general-purpose DRAM to have a data width or a memory organization (for example, ×8, ×16, or ×32) that meets the user's needs. Information of the fuse circuit is read when power is applied to the semiconductor integrated circuit device (i.e., at power on).
Generally, the fuse characteristic is such that the information is reset to the blown state side of the fuse and, by a fuse set signal. The information is inverted to the unblown state side when the fuse is not blown, but remains at the blown state side when the fuse is blown.
However, in the fuse circuit having such a characteristic, the following problem occurs when operating at a low voltage. That is, the lower the voltage at which the fuse circuit is used, the more likely it is that the fuse will be judged to be in the blown state (because of a reduced capability to invert), resulting in the possibility of erroneous information reading. Further, in a circuit that latches the information, as latching at a low voltage is unstable, the information may not be latched correctly.
In the prior art, there is proposed a fuse cell sensing circuit for a flash memory, which is designed to reliably latch fuse cell data, at power on, to a memory cell by determining, using a reference circuit, the setup time for sensing and latching the fuse cell data at power on to the memory cell, and by having the reference circuit track the sensing time that changes due to changes in process (refer, for example, to Patent Document 1).
Patent Document 1
Japanese Unexamined Patent Publication (Kokai) No. 11-283389